The next step is an open chiplet ecosystem and ubiquitous interconnect at the package level.
To satisfy the ever-increasing demand for more computing power, Intel and many of our colleagues in the semiconductor industry have come to the same conclusion: The future of chip innovation lies in moving to modular designs based on “chiplet” building blocks, essentially moving from system-on-chip (SoC) to System-on-Package (SoP) chip architectures.
The feasibility of implementing complex systems on monolithic dies is reaching its physical and economic limits. Gordon Moore predicted this “Day of Reckoning” in his seminal 1965 white paper, “Cramming More Components Onto Integrated Circuits,” writing that as chip density and complexity progressed, eventually “it may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.”
The industry’s increasing adoption of modular semiconductor design takes us into the realm of SoP, giving architects incredible flexibility to mix and match the best IP and process technologies for any given product. Intel has been shipping chiplet-based designs since 2016 with Intel® Stratix®10 FPGAs. Modular design is also a key component of our IDM 2.0 strategy as we use internal and external foundry resources to build our products while offering our foundry services to the industry. Later this year, our customers will see our next-generation tile-based processors in the Sapphire Rapids and Ponte Vecchio SoCs. The success of this future in semiconductor design hinges on there being open standards to enable interoperability throughout the semiconductor supply chain.
In its fullest expression, SoP, chiplet-based architectures allow designers to bring together design IP and process technologies from multiple vendors. But this level of modularity and design freedom will only work if designers are working from standardized, interoperable hardware. We’ve seen this approach work time and again with now-familiar industry specifications including PCIe, CXL and USB. The best way to achieve standardized hardware across multiple vendors is to set a single, open specification that everyone can design to.
That’s why this week, Intel joined forces with Advanced Semiconductor Engineering Inc. (ASE), AMD, Arm, Google Cloud, Meta, Microsoft Corp., Qualcomm Inc., Samsung and Taiwan Semiconductor Manufacturing Co. to launch the Universal Chiplet Interconnect Express (UCIe) consortium. The UCIe consortium is focused on a single goal: creating an open ecosystem for enabling chiplets designed and manufactured on different process technologies by different vendors to work together when integrated with advanced packaging technologies.